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OKI Semiconductor ML7055
Bluetooth Baseband Controller IC
FEDL7055-02
Issue Date: Apr. 8, 2003
GENERAL DESCRIPTION
The ML7055 is a CMOS digital IC for use in 2.4 GHz band BluetoothTM systems. This IC incorporates the ARM7TDMI as the CPU core, features a highly expandable architecture, and supports the interfaces for a variety of applications. Since the ML7055 has Oki's Bluetooth protocol stack software installed, when the IC is used in conjunction with the Bluetooth RF transceiver IC, data/voice communications are possible while maintaining interconnectivity with other Bluetooth systems.
FEATURES
* Conforms to Bluetooth Specification (Ver1.1) * Designed for connection with the RF-LSI interface, such as the OKI RF-LSI interface (ML7050), the SKYWORKS RF-LSI interface (CX72303), or the BROADCOM RF-LSI interface (BCM2002X) that functions as the Bluetooth RF-LSI interface * The high-speed, low-power ARM7TDMITM is installed as the CPU core * PCM-CVSD transcoder that provides high quality voice using the noise filter is installed * Low power consumption in flexible power management modes according to operating modes of Bluetooth * DETACH signal provides control of change to power-saving mode (STOP) and return request to normal mode. * UART interface corresponding to baud rates up to 921.6 kbps * I2C bus interface provides accesses to EEPROM or PCM-Codec * Selactable 12 MHz or 13 MHz for the system clock * Selectable 32 kHz or 32.768 kHz for the LPO clock * Built-in programmed ROM eliminates external ROM/FLASH * The packages are available in three types: 63-pin WCSP for ML7055HB 64-pin BGA for ML7055LA 84-pin BGA for ML7055LP
ARM, ARM7TDMI and Thumb are registered trademarks of ARM Ltd., UK. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc. and licensed to Oki Electric Industry. The information contained herein can change without notice owing to the product being under development.
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SPECIFICATIONS
Process Package 0.16 m CMOS (5-layer metal wire) 63-pin WCSP (P-VFLGA63-4.90x4.72-0.50-W) (Dimensions: 4.90 mm x 4.72 mm x 0.48 mm; pin pitch: 0.50 mm) 64-pin BGA (P-TFBGA64-0707-0.65) (Dimensions: 7 mm x 7 mm x 1.2 mm; pin pitch: 0.65 mm) 84-pin BGA (P-LFBGA84-0909-0.80) (Dimensions: 9 mm x 9 mm x 1.5 mm; pin pitch: 0.80 mm) Supply current Operating voltage ranges Operating frequency Built-in ROM size Built-in RAM size Input clocks RF-LSI interface 22 mA (24 MHz operation) 2.70 to 3.6 V for input-output, 1.65 to 1.95 V for internal circuits 24 MHz 176 KB (for ARM program) 24 KB 12 MHz or 13 MHz (system clock) 32 kHz or 32.768 kHz (LPO clock) OKI RF-LSI interface (ML7050) SKYWORKS RF-LSI interface (CX72303) Installed interfaces BROADCOM RF-LSI interface (BCM2002X) UART interface (up to 921.6 Kbps) General-purpose I/O interface (used as a pin for I2C bus interface depending on software installed) PCM interface (PCM Linear/A-law/-law can be selected) DETACH interface 16-bit auto reload timer (1ch) 18-bit auto reload timer (1ch) Interrupt controller Clock control circuit 11 causes Crystal oscillator circuit (12 MHz or 13 MHz, 32 kHz or 32.768 kHz) Internal PLL
Timers
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PIN PLACEMENT
ML7055HB: 63-pin WCSP (P-VFLGA63-4.90 x 4.72-0.50-W)
RSSI_ TX_POW CLK
8
LVDD
GND
VDD SOUT PLL _CLK
GND Core VDD
GND GND PCM OUT PCM CLK SCL
VDD GND Core VDD GND PCMIN
PLL _PS
7
PLL _POW TXD RSSI
PLL_ DATA GND RX_ POW RXD PLL _OFF PLL_LE SIN
GND
6
GND PCM SYNC
Core VDD
5
VDD
4
PLL SFRQ LOCK SEL
RFSEL1 SDA
XC32KN
3
SCLK SEL RESET AGND0 RFSEL0 CTS CLKOUT VDD VDD DETACH RTS GND
Core XC32KP AVDD1 AGND1 VDD
2
GND
1
AVDD0
GND SCLKN SCLKP GND
Core VDD RFSEL2
A
B
C
D
E
F
G
H
TOP VIEW
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ML055LA: 64-pin BGA (P-TFBGA64-0707-0.65)
GND AGND1 AGND0
10
Core SCLKN RESET VDD GND
GND
RFSEL1
Core VDD RFSEL2 CTS GND SCL Core VDD GND PCM CLK Core VDD GND
XC32KP AVDD1 AVDD0
SCLKP VDD DETACH RFSEL0 RTS CLKOUT SDA VDD PCMIN PCM SYNC PCMOUT
9 XC32KN VDD
8
SCLK SEL
7
SFRQ SEL PLL LOCK RXD
Core VDD
6
RSSI
5
GND
4
TXD
PLL_PS PLL_LE
3
RX_ POW
2
TX_ POW PLL_ OFF
PLL_ DATA RSSI_ CLK
LVDD PLL_ CLK
GND
VDD
GND
GND Core VDD
GND
PLL_ POW
1
GND
SOUT
SIN
GND
VDD
A
B
C
D
E
F
G
H
J
K
TOP VIEW
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ML7055LP: 84-pin BGA (P-LFBGA84-0909-0.80)
Core AVDD1 AGND1 AVDD0 AGND0 SCLKN RESET RFSEL0 VDD RFSEL2 VDD GND NC CTS RTS
GND
10
XC32KP AVDD1 AGND1 AGND0 GND
9
VDD XC32KN
8
NC NC
AVDD0
Core VDD SCLKP DETACH RFSEL1 GND CLKOUT SCL NC SDA VDD Core VDD PCM SYNC Core VDD GND
SFRQ SEL
7
SCLK SEL NC PLL LOCK GND
Core VDD
6
NC
NC
NC
RXD
5
RSSI NC NC PLL_ CLK LVDD GND VDD
PCMIN GND PCMCLK GND NC PCM OUT GND GND
TXD
4
PLL_LE PLL_PS NC
3
TX_ POW
2
RX_ RSSI_ POW CLK PLL_ OFF PLL_ DATA
GND
SOUT
SIN Core VDD
NC
PLL_ POW
1
NC
NC
GND
GND
VDD
A
B
C
D
E
F
G
H
J
K
TOP VIEW
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PIN DESCRIPTIONS
RF I/F
Pin Name Direction [*0] O Internal Pull Up/ Down, Schmitt -- Initial Value L L L -- -- -- X H L L L L L PLL_LE O -- H L Pull down -- -- -- L RSSI_CLK O -- L X H PLL_POW O -- L H H TX_POW O -- L L H RX_POW O -- L L L PLL_PS O -- X L A7 A3 B3 C6 A2 B2 A8 B2 A2 B7 A1 A1 B8 C1 C2 D5 B3 A3 Pin Placement ML7055 HB B6 ML7055 LA B4 ML7055 LP A4 Description ML7050: Transmit data output CX72303: Transmit data output BCM2002X: Transmit data output ML7050: Receive data input CX72303: Receive data input BCM2002X: Receive data input ML7050: Serial write data CX72303: Serial write data BCM2002X: Transmit enable ML7050: Serial clock CX72303: Serial clock BCM2002X: Serial clock ML7050: Serial road enable 0: Negate, 1: Assert CX72303: Serial enable 0: Assert, 1: Negate BCM2002X: RF-LSI synthesizer on 0: Negate, 1: Assert ML7050: Receive field strength data input CX72303: Serial read data BCM2002X: Serial read data ML7050: Receive field strength data clock CX72303: RF-LSI receiving characteristic control BCM2002X: System clock request ML7050: Local PLL power control 0: Assert, 1: Negate CX72303: PA Power control 0: Negate, 1: Assert BCM2002X: Select serial transmit mode ML7050: Transmit enable 0: Assert, 1: Negate CX72303: Transmit enable 0: Negate, 1: Assert BCM2002X: Serial write data ML7050: Receive enable 0: Assert, 1: Negate CX72303: Receive enable 0: Negate, 1: Assert BCM2002X: Receive enable ML7050: "L" CX72303: Power on reset 0: Assert (reset) 1: Negate BCM2002X: RF-LSI receiving characteristic control
TXD
RXD
I
--
C5
B5
A5
PLL_DATA
O
--
C7
C2
C1
PLL_CLK
O
--
E6
D1
D2
RSSI
I
B5
A5
C5
[*0]
"I" = Input, "O" = Output, "I/O" = Input/Output
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RF I/F
Pin Name Direction [*0] Internal Pull Up/ Down, Schmitt Pull down Initial Value -- PLLLOCK I -- -- H PLL_OFF O -- -- L D6 B1 B1 B4 B6 B5 Pin Placement ML7055 HB ML7055 LA ML7055 LP ML7050: -- CX72303: -- BCM2002X: 1MHz clock ML7050: PLL loop control 0: Open loop 1: Closed loop CX72303: Diversity output BCM2002X: PA Power control Description
PCM I/F
Pin Name PCMOUT PCMIN PCMSYNC Direction O I I/O Internal Pull Up/ Down, Schmitt -- Pull up Pull down Initial Value L -- -- Pin Placement ML7055 HB G6 H4 F5 ML7055 LA J3 J5 J4 ML7055 LP J4 H5 K4 Description PCM data output PCM data input PCM sync signal (8 kHz), Initial setting: input (can be switched by an internal register) PCM clock (64 kHz/128 kHz) Initial setting: input (can be switched by an internal register)
PCMCLK
I/O
Pull down
--
G5
K4
H4
Note: The PCM sync signal (8 kHz) must be guaranteed at the accuracy of 50 ppm if the PCMSYNC pin is configured as an input. UART I/F
Pin Name SOUT SIN RTS CTS Direction O I O I Internal Pull Up/ Down, Schmitt -- Schmitt -- -- Initial Value H -- -- H Pin Placement ML7055 HB E7 D4 G2 F3 ML7055 LA F1 G1 J9 K9 ML7055 LP F2 G2 K9 J9 Description ACE transmit serial data ACE receive serial data ACE transmit data ready ACE transmit ready
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CLK and Configuration
Pin Name SCLKP SCLKN XC32KP XC32KN SCLKSEL Direction I O I O I Internal Pull Up/ Down, Schmitt -- -- -- -- Pull down Pull down Initial Value -- -- -- -- -- Pin Placement ML7055 HB E1 D1 A2 A3 B3 ML7055 LA E9 E10 A9 A8 A7 ML7055 LP F8 F10 A9 B8 B7 Description
System clock (12/13 MHz) pins (Power level: CMOS level) Subclock pins (for oscillator) System clock frequency select pin L: Select CLK divided by internal PLL H: Select subclock System clock frequency select pin L: 13 MHz H: 12 MHz RF-LSI select pins RFSEL[2:0] 001: ML7050 (OKI) 010: CX72303 (SKYWORKS) 101: BCM2002X (BROADCOM) Others: Unused Hardware reset pin (Reset = L) Sleep pin (Sleep = L) I2C serial clock I2C serial data System clock (12/13 MHz) output pins
SFRQSEL
I
--
C4
B7
A7
RFSEL0- 2
I
--
--
[*1]
[*2]
[*3]
RESET DETACH SCL SDA CLKOUT
I I O I/O O
Schmitt Schmitt -- -- --
-- -- L H --
C3 F2 G4 F4 G3
F10 G9 K7 J7 J8
G10 G8 H7 K7 K8
[*1] [*2] [*3]
RFSEL0: E3; RFSEL1: E4; RFSEL2: H1 RFSEL0: H9; RFSEL1: H10; RFSEL2: K10 RFSEL0: H10; RFSEL1: H8; RFSEL2: K10
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NC
Pin Name NC Direction Internal Pull Up/ Down, Schmitt Initial Value Pin Placement ML7055 HB -- ML7055 LA -- ML7055 LP [*4] Description No connection
[*4]
B6, C3, C4, C6, C7, C8, D3, E1, F1, H2, H3, H6, H9, J6, J7 Note: Do not wire under the NC pin.
Power, GND
Pin Name VDD CoreVDD LVDD GND AVDD0 AVDD1 AGND0 AGND1 Direction -- -- -- -- -- -- -- -- Internal Pull Up/ Down, Schmitt -- -- -- -- -- -- -- -- Initial Value -- -- -- -- -- -- -- -- Pin Placement ML7055 HB [*5] [*8] C8 [*11] B1 B2 D3 C2 ML7055 LA [*6] [*9] D2 [*12] C9 B9 C10 B10 ML7055 LP [*7] [*10] D1 [*13] [*14] [*15] [*16] [*17] Description I/O power supply pin 2.70 to 3.6 V Power supply pin for internal circuit 1.65 to 1.95 V RF-I/O power suply pin (Same voltage to the VDD for RF-LSI) Digital block ground pin Analog block power supply pin 1.65 to 1.95 V Analog block ground pin
[*5] [*6] [*7] [*8] [*9] [*10] [*11] [*12] [*13] [*14] [*15] [*16] [*17]
VDD: A4, E2, E8, H3, H8 VDD: B8, F2, K1, J6, F9 VDD: A8, F3, K1, K6, F9 Core VDD: A5, D2, F7, G1, H6 Core VDD: A6, H1, K3, K6, J10, D10 Core VDD: A6, G1, K3, K5, J10, E8 GND: A1, A6, C1, D7, D8, F1, F6, F8, G7, G8, H2, H5, H7 GND: A4, A10, D9, E1, E2, G2, G10, H2, J1, J2, K2, K5, K8 GND: A10, B4, E2, E3, E9, G3, G9, H1, J1, J2, J3, J5, J8, K2 AVDD0: D8, D10 AVDD1: B9, B10 AGND0: E10, D9 AGND1: C9, C10
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BLOCK DIAGRAM
CLK GEN Timer System Control APB Ctl AHB Ctl AMBA AHB I/F APB Ctl I/F AMBA APB I/F I/F PCM/ CVSD GPIO UART BT-BB Core I/F I/F I/F DETACH IF IRC Arbiter TIC Default Slave 176kB ROM 24kB RAM IRAMC ARM7 TDMI IROMC
Default Slave
Clock AMBA APB Processor Bus
RFLSI
I/F CTL/ WDT
I/F Timer (1ch)
ML7055
DETACH
UART I/F
GPIO I/F SCL SDA
PCM Codec
FEDL7055-02
ML7055
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DESCRIPTION OF INTERNAL BLOCKS
CLKGEN Block * Generates a clock that is supplied to each block through SCLKP (12/13 MHz) * STOP/HALT function CTL/WDT Block * * * * * Control of the frequency division function of the internal main clock Control of clock supplied to each peripheral Control of reset of each peripheral STOP/HALT control Watchdog timer function (interrupt/reset)
Timer Block * * * * 1 channel 18-bit timer counter Interrupt by compare function One shot, interval, or free-run mode
Base band Core Block
RF LSI Tx SCO Buffer Audio Codec I/F Tx ACL Buffer Packet Composer TXD
Security APB ARM I/F Rx SCO Buffer Rx ACL Buffer
Timing
FHCNT
RF CNT
CNT
Packet Decomposer
RXD
* RF Controller - RF power supply control (PLL, TX, RX) - Local PLL frequency division ratio setting - Receive clock regeneration function - Synchronization detection (synchronizing within the permissable error limit of SyncWord) - Receive clock re-timing function * FH Controller hopping - Sequence control - Frequency hopping selection function - CRC computation's initial value selection function
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* Timing Generator - Bluetooth clock generation - Operation interrupts depend on mode (slot, scan, sniff, hold, park) - Sync detection timing generation (sync window 10 s) - PLL setting timing generation - Transmit/Receive timing generation - Multi-master timing management function * Packet Composer - Access code generation (SyncWord generation, appending PR*TRAILER) - Packet header generation (HEC generation, scrambling, FEC encoding) - Payload generation (CRC generation, encryption, scrambling, FEC encoding) - Packet synthesis * Packet Decomposer - Packet decomposition (separating the packet header and the payload) - Packet header processing (FEC decoding, descrambling, HEC error detection, header information separation) - Payload processing (FEC decoding, descrambling, encryption decoding, CRC judgement, payload separation) * Security - Various key generation functions (initialization, link key, encryption key) - Certification function - Encryption function
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UART Block * * * * * * * * * * Full-duplex buffering method All status reporting function Built-in 64-byte transmit/receive FIFO Modem control based on CTS Programmable serial interface 5-, 6-, 7-, 8-bit characters Generation and verification of odd parity, even parity, or no parity 1, 1.5, or 2 stop bits Programmable Baud Rate Generator (9600 bps to 921.6 kbps) Error servicing for parity, overrun, and framing errors
* Configuration of 1 Data Frame during Reception
SIN SAMPLE CLK
5 data bits to 8 data bits
Start
Parity
Stop
* Configuration of 1 Data Frame during Transmission
SOUT
Start 5 data bits to 8 data bits Parity Stop
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PCM-CVSD Transcoder Block * Application side I/O: - PCM Codec * Application-side format: - PCM linear (8, 14, 16 bits/sample, 8 kHz sampling frequency)/A-law/-law * Bluetooth-side format: - CVSD/A-law/-law * All combinations of the above conversions are supported * PCMSYNC/PCMCLK I/O can be switched (initial setting: input) * Timing in Short Mode and in PCMCLK and PCMSYNC Output Mode (For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits PCMCLK(O)
64k/128kHz
PCMOUT
LSB
MSB
DATA
DATA
DATA
LSB
MSB
DATA
Data is output on the rising edge of CLK. PCMIN PCMSYNC(O) LSB MSB DATA DATA DATA LSB MSB DATA
Data is shifted in on the falling edge of CLK
125s (8kHz)
* Timing in Short Mode and in PCMCLK and PCMSYNC Input Mode. (For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits PCMCLK(I)
64k/128kHz
PCMOUT
LSB
MSB
DATA
DATA
DATA
LSB
MSB
DATA
Data is output on the rising edge of CLK. PCMIN PCMSYNC(I) LSB MSB DATA DATA DATA LSB MSB DATA
Data is shifted in on the falling edge of CLK
125s (8kHz)
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* Timing in Long Mode and in PCMCLK and PCMSYNC Output mode (For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits
PCMCLK(O)
64k/128kHz
PCMOUT
MSB
DATA
DATA
DATA
DATA
LSB
MSB
DATA
Data is output on the rising edge of CLK PCMIN PCMSYNC(O) PCMCLK period x 3 125s (8kHz) MSB DATA DATA DATA
Data is shifted in on the falling edge of CLK DATA LSB MSB DATA
* Timing in Long Mode and in PCMCLK and PCMSYNC Input Mode. (For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits
PCMCLK(I)
64k/128kHz
PCMOUT
MSB
DATA
DATA
DATA
DATA
LSB
MSB
DATA
Data is output on the rising edge of CLK. PCMIN MSB DATA DATA DATA
Data is shifted in on the falling edge of CLK. DATA LSB MSB DATA
PCMCLK period (Min.) or 62.5 s (Max.) 125s (8kHz)
DETACH Interface Block * Generation of the request for change to (from) the stop mode by detection of the rising (falling) edge of the DETACH signal
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ABSOLUTE MAXIMUM RATINGS
Parameter I/O power supply voltage Core power supply voltage Input voltage Allowable power dissipation Storage temperature Symbol VDD/LVDD CoreVDD/AVDD VI Pd Tstg Conditions -- -- -- -- -- Rating -0.3 to +4.5 -0.3 to +2.5 -0.3 to +4.5 0.62 -55 to 150 Unit V V V W C
RECOMMENDED OPERATING CONDITIONS
Parameter I/O power supply voltage Core power supply voltage "H" level input voltage "L" level input voltage Operating temperature Symbol VDD/LVDD CoreVDD/AVDD Vih Vil Ta Conditions -- -- -- -- -- Min. 2.7 1.65 2.2 0 -40 Typ. 3.3 1.8 -- -- -- Max. 3.6 1.95 VDD 0.8 85 Unit V V V V C
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 to 3.6 V, CoreVDD = 1.65 to 1.95 V, Ta = -40 to +85C) Parameter "H" level output voltage "L" level output voltage Symbol Voh Vol Ioh = -2 mA Conditions 3.0VVdd3.6V 2.7VVdd<3.0V Iol = 2 mA Vi = GND to 3.6 V Vi = VDD Input leakage current Ii 50 k Pull-down Vi = GND 50 k Pull-up Vo = GND to VDD Output leakage current Power supply current (during operation) Power supply current (during stand-by) Io Vo = VDD 50 k Pull-down Iddo Idds During 24 MHz operation CLK stopped Min. 2.4 2.2 -- -10 10 -200 -10 10 0 -- Typ. -- -- -- -- 66 -66 -- 66 22 10 Max. -- -- 0.4 10 200 -10 10 200 32 100 A A Unit V V
mA A
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Power Supply Current (IDDO) Characteristics by Power Saving Mode
(VDD = 2.7 V to 3.6V, CoreVDD = 1.65 V to 1.95V, Ta = -40 to 85C) Operating mode STOP mode (DETACH = "L") Page Scan operating mode Poll Interval operating mod Sniff operating mode Hold operating mode Conditions -- Interval:1.28sec Window:11.25msec Interval:40slot Interval:2000slot Attempt:4frame Interval:4000slot DH1/DM1 ACL operating mode RX:DH3/DM3 TX:DH1/DM1 RX:DH5/DM5 TX:DH1/DM1 Min. -- -- -- -- -- -- -- -- Typ. 0.03 2.5 3.5 2.5 0.05 22.0 22.0 22.0 Max. -- -- -- -- -- -- -- -- mA Unit
AC Characteristics System clock (SCLKP) SCLKP
Tmc0 Tmc1
Parameter Tmc0 Tmc1
(VDD = 2.7 to 3.6V, CoreVDD = 1.65 to 1.95V, Ta = -40 to 85C) Description Min Typ Max Unit Duty in SCLKP "H" duration 40 50 60 % Duty in SCLKP "L" duration 40 50 60 %
Sub-clock (XC32KP)
XC32KP
Tmp0 Tmp1
Parameter Tmp0 Tmp1
(VDD = 2.7 to 3.6V, CoreVDD = 1.65 to 1.95V, Ta = -40 to 85C) Description Min Typ Max Unit Duty in XC32KP "H" duration 40 50 60 % Duty in XC32KP "L" duration 40 50 60 %
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Reset
Power supply stable period
Vdd/LVdd
CoreVdd/AVdd
TRESW RESET
Parameter TRESW
Reset pulse width
(VDD = 2.7 to 3.6V, CoreVDD = 1.65 to 1.95V, Ta = -40 to 85C) Description Min Typ Max Unit 10 -- -- s
Note : Apply "L" to the RESET pin for 10 sec or more after the power supply has been settled.
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PCM interface
PCMCLK(I) PCMIN
Tpc0 Tpc1 Tpc2
PCMOUT
Tpc2
PCMSYNC(I)
Tpc3 Tpc4 Tpc3 Tpc4
PCMCLK(O) PCMIN
Tpc5 Tpc6
PCMOUT
Tpc 7 Tpc7
PCMSYNC(O)
Tpc 8
Parameter Tpc0 Tpc1 Tpc2 Tpc3 Tpc4 Tpc5 Tpc6 Tpc7 Tpc8
(Vdd = 2.7 to 3.6V, CoreVdd = 1.65 to 1.95V, Ta = -40 to 85C) Description Min Typ Max Unit PCMIN setup time relative to PCMCLK (input) falling edge 100 ns -- -- PCMIN hold time relative to PCMCLK (input) falling edge 100 ns -- -- PCMOUT delay time relative to PCMCLK (input) rising edge 250 ns -- -- PCMSYNC (input) setup time relative to PCMCLK (input) -- -- 100 ns rising edge PCMSYNC (input) hold time relative to PCMCLK (input) -- -- ns 100 rising edge PCMIN setup time relative to PCMCLK (output) falling edge 100 ns -- -- PCMIN hold time relative to PCMCLK (output) falling edge 100 ns -- -- PCMOUT delay time relative to PCMCLK (output) rising -- 250 ns -- edge Delay time from PCMCLK (output) rising edge to PCMSYNC 150 ns -- -- (output)
AC Characteristic Measuring Points
VDD 0.8VDD 0.2VDD 0.8VDD 0.2VDD
0V
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REFERENCE FOR VOLTAGE SUPPLY CIRCUIT
ML7055
AVDD0 0.1F AGND0 AVDD1 0.1F AGND1
CoreVDD
10 to 47F
0.1F
0.1F
CoreVDD
LVDD
10 to 47F
0.1F
0.1F
VDD 10 to 47F GND 0.1F 0.1F
VDD GND
Capacitors should locate close to LSI pins.
Feed lines should be separated from LSI pins.
Example of ML7055 voltage supply circuit * Insert appropriate bypass capacitors between the VDD and GND lines. Note 1: Precautions to insert the bypass capacitors - Use traces of VDD and GND lines wider than those of the other signal lines. - Keep the length of traces between the bypass capacitors and the VDD line and between the bypass capacitors and the GND line as short as possible. - Keep the length of traces between the bypass capacitors and the VDD line and between the bypass capacitors and the GND line as equal as possible. The circuit is subject to change according to the specific LSI board design. Please contact Oki Electric Industry Co., Ltd. for detailed information.
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REFERENCE FOR OSCILLATOR CIUCUIT
ML7055
XC32KP
XC32KN
R0 R1
SCLKP
R2 R3
C0
X'tal 1
C1
C2
X'tal 2
SCLKN C3
Connect this oscillator circuit only when connecting the OKI RF-LSI ML7050.
Example of oscillator circuit Note 1: The values of C0 and C1, and R0 and R1 should be determined according to the specifications for the external crystal X'tal 1 (32 or 32.768 kHz). The values of C2 and C3, and R2 and R3 should be determined according to the specifications for the external crystal X'tal 2 (13 or 12 MHz). Note 2: The crystal oscillator circuit should be connected to pins SCLKP and SCLKN only when the OKI RF-LSI (ML7050) is connected. In other cases, the system clock should be input from the RF-LSI to pin SCLKP. Note 3: In the case of 13 MHz or 12 MHz system clock (SCLKP) input, make sure the crystal frequency tolerance is 20 ppm for temperature, supply voltage, and aging. In the case of 32 kHz or 32.768 kHz sub-clock (XC32KP) input, make sure the crystal frequency tolerance is 250 ppm for temperature, supply voltage, and aging. Note 4: Precautions to build a crystal oscillator circuit - Keep length of wire traces as short as possible. - Do not cross the crystal oscillator circuit wires over other signal line wires. - Do not keep signal line wires through which high current flows close to the crystal oscillator circuit. - Keep the grounding point of the capacitors in the oscillator circuit at the potential equal to GND. And do not connect the capacitors to the GND or GND lines through which high current flows. - Do not output signals from the oscillator circuit. The circuit is subject to change according to the specific LSI board design. Please contact Oki Electric Industry Co., Ltd. for detailed information. It is recommended to determine the final circuit values including the capacitance of the circuit board designed by the user.
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ML7055
APPLICATION NOTES
Clock Selection * The system clock frequency is selected according to external pin SFRQSEL. SFRQSEL = 0 : SFRQSEL = 1 : A 13 MHz clock is input to external pins SCLKP. A 12 MHz clock is input to external pins SCLKP.
* The CPU clock supply source is selected according to external pin SCLKSEL. SCLKSEL = 0 : Use the clock that was divided down from the internal PLL output of 192 MHz that was generated from external pins SCLKP. (Dividing ratios are selectable in the range of 1/6 to 1/16. Initial value is 1/8 (24 MHz).) Use external pins XC32KP.
SCLKSEL = 1 :
Note: The clock supply source can be set by the CLKCNTL register in the CTL/WDT block once the LSI is powered up. * The frequency of CPU clock is selectable from the high speed (24 MHz) and low speed (16 MHz). This can be performed by the Vendor Specific Command. Setting the Reset * Apply a "L" level to the RESET pin for more than 10 s after power voltage is stabilized. When the system clock oscillator circuit is stable and the RESET pin is at a "H" level, the internal reset is released and operation starts after the internal reset is held for 1.9 ms for the input clock of 13 MHz or 2.0 ms for the input clock of 12 MHz. Setting the UART Baud Rate * It is possible to set the UART baud rate using the Vendor Specific Commands. Available baud rate settings: 9600/19.2k/38.4k/56k/57.6k/115.2k/230.4k/345.6k/460.8k/921.6k (Initial value is 115.2 kbps.) Setting the PCM-CVSD Transcoder * It is possible to set the PCM-CVSD transcoders using the Vendor Specific Commands. For command details, contact Oki Electric Industry Co., Ltd. * It is possible to set the following parameters using the VCCTL command: - PCMSYNC/PCMCLK mode (initial setting: input) - Mute reception (initial setting: OFF) - Mute transmission (initial setting: OFF) - Air coding CVSD (initial setting)/-law/A-law - Interface coding Linear (initial setting)/-law/A-law - PCM format (data width of one PCM Linear sample) 8-bit (initial setting)/14-bit/16-bit - Serial interface format Short frame (initial setting)/long frame
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ML7055
- Application interface mode PCM Codec I/F (initial setting)/APB I/F XTAL Input Frequency of BCM2002X * If the system clock is supplied from BCM2002X, the XTAL input frequency of BCM2002X must be 13 MHz. 12, 19.2, 19.68, or 19.8 MHz should not be applied. XTAL Input Frequency of CX72303 * If the system clock is supplied from CX72303, the XTAL input frequency of CX72303 must be 13 MHz. 10 MHz should not be applied. Required processes when interface pins are unused * The following tables show the processes that should be performed when interface pins are not used. * The pins that are not included in the following table should be left open. RF I/F
Pin Name RXD RSSI PLLLOCK Process When Pin Not Used GND Open or GND Open or GND Comments
UART I/F
Pin Name SIN CTS Process When Pin Not Used VDD GND Comments
PCM I/F
Pin Name PCMIN PCMSYNC PCMCLK Process When Pin Not Used Open or VDD Open or GND Open or GND Comments
Processes of Other Pins TEST I/F etc.
Pin Name DETACH Process When Pin Not Used Pull up or VDD Comments
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OKI Semiconductor
System Configuration Example ML7055/ML7050 VDD
Poewr on reset Hardware reset Microphone Voice input/ output peripherals Speaker PCMIN PCMOUT RSYNC XSYNC BCLK MSM7702-01
68k
ML7055 RESET LVDD
47
VDD
RFVDD
ML7050
0.1
0.1
VDD_D
ANT
PCMOUT PCMIN PCMSYNC PCMCLK
RXD PLL_LE PLL_DATA PLL_CLK PLL_OFF TXD PLL_POW RX_POW TX_POW RSSI RSSI_CLK PLL_PS PLLLOCK CLKOUT SCLKN
GND
RXD PLL_LE PLL_DATA PLL_CLK PLL_OFF TXD PLL_POW RX_POW TX_POW
MCLK
SCLKSEL SFRQSEL
VDD VDD
13MHz 20ppm
SCLKP XC32KN
GND
RFSEL2 RFSEL1 RFSEL0
GND
68k
DETACH AVDD0
0.1
XC32KP
32kHz or 32.768kHz 250ppm
GND
AGND0
Separate, as far as possible, the wiring from the board pins.
CoreVDD GND
SOUT RTS SIN CTS
AVDD1
0.1
T1IN T1OUT T2IN T2OUT T3IN R1OUT R1IN R2OUT R2IN
GND
TD RTS 1 2 3 4 5 6 7 8 9 GND
UART I/F
RD CTS
DSUB9PIN
AGND1
VDD
MAX3245
CoreVDD
VDD 0.1 0.1 47 47k
VDD
VDD
0.1 0.1 47
SDA SCL
SDA SCL
Vcc
GND
GND
GND
GND
The capacitors should be as close to the LSI pins as possible.
NC
AT24C02
FEDL7055-02
ML7055
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OKI Semiconductor
ML7055
PACKAGE DIMENSIONS
ML7055HB - 63pinWCSP (P-VFLGA63-4.90 x 4.72-0.50-W)
(Unit: mm)
P-VFLGA63-4.90x4.72-0.50-W
5
Package material Terminal material Package weight (g) Rev. No./Last Revised
Epoxy resin Sn/Pb 0.03 TYP. 1/May 27, 2002
Note: A lead-free package is available. Please contact Oki Sales Office/Distributors for more information.
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FEDL7055-02
OKI Semiconductor
ML7055
ML7055LA - 64pinBGA (P-TFBGA64-0707-0.65)
(Unit: mm)
P-TFBGA64-0707-0.65
5
Package material Ball material Package weight (g) Rev. No./Last Revised
Epoxy resin Sn/Pb 0.10 TYP. 1/July 5, 2002
Note: A lead-free package is available. Please contact Oki Sales Office/Distributors for more information.
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FEDL7055-02
OKI Semiconductor
ML7055
ML7055LP - 84pinBGA (P-LFBGA84-0909-0.80)
(Unit: mm)
P-LFBGA84-0909-0.80
5
Package material Ball material Package weight (g) Rev. No./Last Revised
Epoxy resin Sn/Pb 0.20 TYP. 1/May 15, 2000
Note: A lead-free package is available. Please contact Oki Sales Office/Distributors for more information. Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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ML7055
REVISION HISTORY
Document No.
PEDL7055-01
Date
Aug.23, 2002
Page Previous Current Edition Edition
-1 --1 2
Description
Preliminary edition 1 The contents of the "FEATURES" Section have been fully changed. Added the "SPECIFICATIONS" Section. The contents of the table in the "ABSOLUTE MAXIMUM RATINGS" Section have been partially changed. The voltage values of "Core VDD" have been added on the table in the "DC Characteristics" Section. The pin name has been changed from LPO_CLK to TCK. Eliminated the "LPO_CLK" row in the table of the "RF/IF" Section. Eliminated "Note" on the bottom side of the table of the "RF/IF" Section.
2
3
3
4
5
6
PEDL7055-02
Nov. 25, 2002 6 7
The "Description" column of Pin name "TCK" in the table of the "JTAG I/F" Section has been partially changed. Added "REFERENCE CIRCUIT" Section. FOR OSCILLATOR
8
9
11
13
"DETACH signal" has been changed to "DETECH signal" in the content of the "DETACH Interface Block" Section. Eliminated the "RESET signal input" Section and added the "Setting the Reset" Section. The "XTAL Input Frequency of BCM2002X" and "XTAL Input Frequency of CX72303" Sections have been added. Eliminated the "LPO_CLK" row of the "Pin name" column in the table of the "RF/IF" Section.. Changed the System Configuration Examples. Partially changed the contents of "FEATURES" Section. Changed the contents of "Package" row in the table. Partially added the contents of "UART Block" Section. Partially added the contents of "PCM-CVSD" Section.
12
14
--
15
13 14-16 1 FEDL7055-01 Dec. 17, 2002 2 13 13
15 16-18 1 2 13 14
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FEDL7055-02
OKI Semiconductor
ML7055
Document No.
Date
Page Previous Current Edition Edition
13 15
Description
Partially eliminated the contents of "DETACH Interface Block" Section. Added "Power Supply Current Characteristics by Power Saving Mode" and "AC Characteristics" Sections. Partially added the contents of "REFERENCE FOR VOLTAGE SUPPLY CIRCUIT" Section. Partially added the contents of "REFERENCE FOR OSCILLATOR CIRCUIT" Section. Partially added the contents of "Clock Selection" Section. Partially changed the contents of "System Configuration Example" Section. Partially added the contents of "RF I/F" Section. Partially added the Characteristics" Section. contents of "DC
--
17-19
9 FEDL7055-01 Dec. 17, 2002 10 14 16 6 16 FEDL7055-02 Apr. 8, 2003 18 23
19 20 22 24 6 16 18 23
Partially eliminated the contents of "Reset" Section. Eliminated the "RESET" row in the table of the "TEST I/F " Section.
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ML7055
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2003 Oki Electric Industry Co., Ltd.
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